Although applicable in principle to any desired integrated circuits, the present invention and the problem area on which it is based are explained with regard to integrated memory circuits using silicon technology.
FIGS. 2a–c show schematic illustrations of successive method stages of a method for fabricating a semiconductor structure in order to illustrate the problem area according to the invention.
In FIG. 2a, reference symbol 1 designates a silicon semiconductor substrate into which elements (not illustrated in any specific detail) of a semiconductor memory circuit are integrated. Reference symbol 5 is a gate dielectric layer made of silicon oxide. Over the gate dielectric 5, provision is made of a layer sequence made of a bottommost layer 10 made of polysilicon, a second from bottom layer 15 made of WN, a third from bottom layer 20 made of W and a topmost layer made of silicon nitride.
Partly finished elongate, essentially parallel gate stacks GS1, GS2 have been etched into the layer sequence by means of a customary etching method. In this case, the bottommost layer 10 has been thinned merely to a reduced thickness h″ in comparison with its original thickness h′. In other words, the gate stacks GS1, GS2 have not yet been completely separated from one another in the process state shown in FIG. 2a. In the example shown, the thickness h″ is approximately half as large as the thickness h′.
In a subsequent process step, illustrated in FIG. 2b, sidewall spacers 30 made of silicon nitride are formed on the vertical sidewalls of the semifinished gate stacks GS1, GS2, said sidewall spacers typically having a thickness of 5 nm in 90 nm technology.
After the process state shown in FIG. 2b, the structure is etched anisotropically using the sidewall spacers 30 as a mask, the polysilicon that is uncovered between the semifinished gate stacks GS1, GS2 above the dielectric 5 being removed in order to completely separate the gate stacks GS1, GS2.
In a further method step, the uncovered lateral surface of the bottommost layer 10 made of polysilicon is then selectively oxidized in order to create sidewall oxide regions 50 as insulation there.
What is problematic about the semiconductor structure described with reference to FIGS. 2a–c is that the layers 15, 20 made of WN and W, respectively, on the one hand have a high contact resistance with respect to the layer 10 made of polysilicon and word line/bit line short circuits often occur.
The high contact resistance stems from an inadequate protection from oxygen diffusion through the thin spacers, and the word line/bit line short circuits stem from the fact that the polysilicon 10 of the bottommost layer 10 projects laterally outward below the spacers 30 and, therefore, only a very thin insulation made of the sidewall oxide region 50 is present there.